1. Field of the Invention
The present invention relates to a method of forming a gate insulation film using plasma, and more particularly, to a method of forming a gate insulation film using plasma, and a method of fabricating a poly-silicon thin film transistor using the same, which can enhance an interfacial feature which exists between the gate insulation film and a silicon thin film and which is fatal to performance of the thin film transistor.
2. Description of the Related Art
In general, a silicon nitride film or a silicon oxide film as a gate insulation film is deposited on a silicon thin film by a PECVD (Plasma Enhanced Vapor Deposition) method when a thin film transistor is fabricated. In the case of an amorphous silicon thin film transistor, crystallization of a silicon thin film does not vary by the following processes. In the case of a laser or high-temperature poly-silicon thin film transistor, an amorphous silicon thin film is poly-crystallized in advance prior to depositing a gate insulation film. Accordingly, there is no physical/chemical change on an interfacial surface between the gate insulation film and the silicon thin film after having formed the gate insulation film.
However, an amorphous thin film transistor is worked by a metal induced lateral crystallization (MILC) method to thus form a poly-crystallization thin film transistor. Thereafter, a change in volume of a silicon thin film occurs at a crystallization process of crystallizing an amorphous silicon thin film. Thus, a physical/chemical change is induced on the interfacial surface between the gate insulation film and the silicon thin film which have been formed before.
A conventional method of fabricating a poly-crystallization thin film transistor using a MILC method will follow.
FIGS. 1A through 1D are cross-sectional views for explaining a conventional low-temperature poly-silicon thin film transistor fabrication method using a MILC method, respectively.
Referring to FIG. 1A, a buffer layer 10 made of an oxide film is formed on an insulation substrate such as a glass substrate (not shown), and then an amorphous silicon film is formed on the buffer layer 10. Then, the amorphous silicon film is patterned by a photographic etching process to thereby form a semiconductor layer 11, and subsequently, an insulation film and a metal film are deposited on a substrate by a PECVD (Plasma Enhanced Vapor Deposition) method and a sputtering method, respectively, and then patterned by the photographic etching process, to thereby form a gate electrode 13 and a gate insulation film 12.
Then, referring to FIG. 1B, a source region 11S and a drain region 11D are formed through an ion injection process of injecting impurities. Then, as shown in FIG. 1C, an off-set structure is formed using a photosensitive agent pattern 14. Then, a nickel (Ni) film 15 is deposited on the entire substrate surface with crystallization expediting metal for performing metal induced lateral crystallization (MILC).
Referring to FIG. 1D, the photosensitive agent pattern 14 is removed by using a lift-off method, and then a heat treatment is performed at a temperature between 400° C. through 600° C. Accordingly, in the case of a source and drain regions 11S and 11D which contact a nickel (Ni) film 15, amorphous silicon is crystallized into poly-silicon by metal induced crystallization (MIC), while in the case of portions which do not contact the Ni film 15, that is, in the case of exposed off-set regions 16a and 16b and a channel region 11C, amorphous silicon is crystallized into poly-silicon by metal induced lateral crystallization (MILC).
As described above, in the case of a conventional thin film transistor fabrication method of transforming amorphous silicon into poly-silicon using the MILC method, crystallization of amorphous silicon is performed after forming the gate insulation film 12. Thus, a physical/chemical change is induced on an interfacial surface between the gate insulation film and the silicon thin film at the time of crystallization due to a change in volume of silicon.
That is, in the case that an oxide film is directly deposited on amorphous silicon as an insulation film, a dangling bond of silicon which is not completely oxidized and bonded on a silicon/oxide film interfacial surface may exist. This functions as a trap for capturing a carrier passing through a transistor channel to thereby deteriorate features of a device, in particular, deteriorate a junction capability between an upper oxide film and a silicon film at the time of crystallizing amorphous silicon.
A physical/chemical change occurring on the interfacial surface makes a big influence upon electrical characteristics of a transistor such as a leakage current, an electron mobility, and an on/off ratio. Thus, a new process need to be developed in order to minimize a bad influence affecting on electrical characteristics of a transistor by the physical/chemical change.